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PhD Defence: Test Cost Reduction of 3D Stacked ICs (Breeta Sengupta)

Disputation

From: 2020-09-04 09:00
Place: E:1408, building E, John Ericssons väg 2, Lund.  / Zoom: https://lu-se.zoom.us/j/66036051217
Contact: erik [dot] larsson [at] eit [dot] lth [dot] se
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Date: 2020-09-04 at 9:00

Location: E:1408, building E, John Ericssons väg 2, Lund.  / Zoom: https://lu-se.zoom.us/j/66036051217

Oponent: Prof. Adit Singh, Aburn University, USA

Abstract: Ever higher levels of integration within the Integrated Circuit (IC) to meet progressively widening scope of its application in respect of functionality,
size, performance and manufacturing issues inspired development of the three-dimensional (3D) Stacked IC as a device having viable architecture. However, with increased complexity, manufacturing cost increased. The manufacturing cost includes the test cost component, essential to ensure fidelity to the desired design specifications. Of the several challenges faced by 3D Stacked ICs, cost efficient testing of the manufactured product is most critical. Reduction of test cost for 3D Stacked ICs through test planning along with test flow selection methods is addressed in this thesis.

Test planning for 3D Stacked ICs is performed by reducing the total cost accounting for the test time and Design-for-Test (DfT) hardware. Three test architecture standards are used: Built-In Self-Test (BIST), IEEE 1149.1 and IEEE 1500. The test cost corresponding to each test architecture is detailed and test planning algorithms are proposed. The algorithms are implemented and experiments are performed on several 3D Stacked IC designs formed with multiple 2D IC benchmarks. For experiment, a test flow is presented that comprises the wafer test of each chip followed by test of the entire packaged IC. Results indicate effectiveness of the proposed algorithms in terms of test cost. Test flow selection, to decide stages at which tests are to be performed, for 3D Stacked ICs is addressed motivated towards the reduction of test time required to produce each single fault-free package. A model to calculate the total test time for any given test flow is detailed. An algorithm is proposed to find a test flow for reducing test time. The algorithm is implemented and executed on several 3D Stacked IC designs with up to ten chips in the stack. Results indicate considerable reductions in test time as compared to predetermined test flows.