Thesis defence: III-V Devices for Emerging Electronic Applications
Place: E-house, E:1406.
Contact: patrik [dot] olausson [at] eit [dot] lth [dot] se
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Patrik Olausson defends his thesis (III-V Devices for Emerging Electronic Applications) 23rd of February.
Today’s digitalized society relies on the advancement of silicon (Si) Complementary Metal Oxide Semiconductor (CMOS) technology, but the limitations of down-scaling and the rapidly increasing demand for added functionality that is not easily achieved in Si, have pushed efforts to monolithically 3D-integrate III-V devices above the Si-CMOS technology. In addition, the demand for increased computational power and handling of vast amounts of data is rapidly increasing. This has led to an increased interest in quantum computing, offering the potential to solve specific complex problems more efficiently than conventional computers. Superconducting transmon Quantum Bits (qubits) are promising for the realization of quantum computers, which has led to an increased interest in cryogenic electronics. For these applications, III-Vs are suitable as their high carrier mobility enables low power consumption, low noise, and highly transparent superconductor-semiconductor interfaces. High-quality interfaces between superconductors and semiconductors are crucial for the implementation of gate-tunable hybrid superconductor-semiconductor qubits known as gatemon qubits.
This thesis explores the potential of utilizing indium arsenide (InAs) and indium gallium arsenide (InGaAs) nanowire and quantum well devices in these emerging electronic applications. Both as an add-on in Si-CMOS technology, as well as the channel material in electronic devices for cryogenic applications.
The electron transport in near surface quantum wells is studied by DC-measurements in combination with applied magnetic fields, from room temperature down to cryogenic temperatures. Several different ways to extract the carrier mobility are investigated, such as standard current-voltage sweeps, the Geometrical Magnetoresistance Effect (gMR), as well as the Hall effect. A deeper understanding of electron transport at cryogenic temperatures is obtained by the development of a model for the current characteristics of long-channel InGaAs quantum well Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs), which includes the effects of band tail states, electron concentration-dependent mobility, and interface trap density. The model shows an increased effect of remote impurity scattering associated with mobility degradation in the subthreshold region.
A demultiplexer based on an InGaAs nanowire network was fabricated, to enable routing of DC-currents on-chip and reduce the number of connections to the cryostat. To facilitate system-level investigation of circuits containing Josephson Field-Effect Transistors (JoFETs), a compact model was developed which by circuit simulations accurately reproduced the measured data from our JoFET.
Finally, a process for the growth of InAs nanowires on tungsten was developed. This novel approach is based on Template-Assisted Selective Epitaxy (TASE) and allows for easy 3D-integration of III-V devices in Si-CMOS technology.
Link to thesis i LU Research Portal: