PhD defence: High-Speed Analog-to-Digital Converters in CMOS
Place: Online at Zoom and Lecture hall E:B, building E, Ole Römers väg 3, Faculty of Engineering LTH, Lund University, Lund
Contact: pietro [dot] andreani [at] eit [dot] lth [dot] se
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Author: Siyu Tan, Department of Electrical and Information Technology, LTH, Lund University
Faculty opponent: Prof. Piero Malcovati from the University of Pavia, Italy
Supervisor: Pietro Andreani, Department of Electrical and Information Technology, LTH, Lund University
Location: Online - link by registration
Please register at https://www.lth.se/digitalth/events/register-2020-12-18/ in order to get an access link to the online meeting.
The Analog to Digital (A/D) Converters (ADC) are vital components in high-performance radio devices. In the receiver end, the signal received by the analog front-end can not be directly analyzed by the digital core, thus requiring high-performance ADC circuits acting as bridges connecting the analog and digital domain. These circuits are integrated into Complementary Metal-Oxide-Semiconductor (CMOS) chips, which achieve high performance and consume low power at the same time.
In this research, various types of ADCs are analyzed both in architectural designs and component-level implementations. The goal is to find out optimized circuit designs to be used in high-speed communication devices in the future.
Two Successive-Approximation-Register (SAR) ADCs are studied. One of the SAR ADCs is a previously designed synchronous SAR ADC CMOS chip, implemented in the 22nm Fully Depleted Silicon On Insulator (FD-SOI) CMOS, whose measurement results are shown. An estimation and calibration technique for linearizing its Digital to Analog Converter (DAC) imbalance is presented.
Another SAR ADC is improved from the synchronous version, which has asynchronously clocked internal components, designed and implemented in 22nm FD-SOI. Two Continuous-Time (CT) ΔΣ ADCs were designed and analyzed. One of the ΔΣ ADCs is a high-speed converter implemented in 28nm FD-SOI CMOS, running at 5GHz sampling frequency and targeting at 250MHz signal bandwidth. Another ΔΣ ADC is implemented in 65 nm CMOS and fabricated. It evaluates the effectiveness of digital calibration techniques in linearizing a critical outer-most DAC in the feedback.
All the ADC designs showing in this work are closely related to the state-of-the-art research works. The design specifications from the industry field are also carefully considered during the design phase. The introductions and the design details are explained in the first part of this dissertation, and the relevant research papers are attached in the second part.