Electrical and Information Technology

Faculty of Engineering, LTH

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PhD defence: III-V Nanowire MOSFET High-Frequency Technology Platform (Stefan Andric)

Graph over high-frequency circuit, compiled using device and circuit component models, illustrating the unique scaling capabilities of the novel nanowire devices. Illustration.
Summary of the technology platform: high-frequency circuit, compiled using device and circuit component models, illustrating the unique scaling capabilities of the novel nanowire devices.


From: 2021-05-28 09:15 to 12:00
Place: E:1406 and / or online
Contact: lars-erik [dot] wernersson [at] eit [dot] lth [dot] se
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Thesis title: III-V Nanowire MOSFET High-Frequency Technology Platform

Author: Stefan Andric, Department of Electrical and Information Technology, Lund university

Faculty opponent: Professor Ingmar Kallfass 

Location: Online from  Room E:1406, LTH - Access link by registration


The thesis addresses the main challenges in using III-V nanowire MOSFETs for high-frequency applications by building a III-V
vertical nanowire MOSFET technology library. The initial device layout is designed, based on the assessment of the current III-V vertical nanowire MOSFET with state-of-the-art performance. The layout provides
an option to scale device dimensions for the purpose of designing various high-frequency circuits. The nanowire MOSFET device is described using 1D transport theory, and modeled with a compact virtual source model. Device assessment is performed at high frequencies, where sidewall spacer overlaps have been identified and mitigated in subsequent design iterations. In the final stage of the design, the device is simulated with fT > 500 GHz, and fmax > 700 GHz.

Alongside the III-V vertical nanowire device technology platform, a dedicated and adopted RF and mm-wave back-end-of-line (BEOL) has been developed. Investigation into the transmission line parameters reveals a line attenuation of 0.5 dB/mm at 50 GHz, corresponding to state-ofthe-art values in many mm-wave integrated circuit technologies. Several key passive components have been characterized and modeled. The device interface module - an interconnect via stack, is one of the prominent components. Additionally, the approach is used to integrate ferroelectric MOS capacitors, in a unique setting where their ferroelectric behavior is captured at RF and mm-wave frequencies.

Finally, circuits have been designed. A proof-of-concept circuit, designed and fabricated with III-V lateral nanowire MOSFETs and mm-wave BEOL,validates the accuracy of the BEOL models, and the circuit design. The device scaling is shown to be reflected into circuit performance, in a unique device characterization through an amplifier noise-matched input stage. Furthermore, vertical-nanowire-MOSFET-based circuits have been designed with passive feedback components that resonate with the device gate-drain capacitance. The concept enables for device unilateralization and gain boosting. The designed low-noise amplifiers have matching points independent on the MOSFET gate length, based on capacitance balance between the intrinsic and extrinsic capacitance contributions, in a vertical geometry. The proposed technology platform offers flexibility in device and circuit design and provides novel III-V vertical nanowire MOSFET devices and circuits as a viable option to future wireless communication systems

The thesis for download as PDF


The event is open to anyone interested. If you register at we send you a link for the event at the zoom platform.