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PhD Defence: Electrical Characterisation of III-V Nanowire MOSFETs (Markus Hellenbrand)

View on a transistor sample through a microscope.
View on a transistor sample through a microscope. The black tips are the electrical contacts of the measurement setup

Disputation

From: 2020-06-12 09:15
Place: E:1406, E-building, Ole Römers väg 3, LTH, Lund University / Zoom: https://lu-se.zoom.us/j/64523497259
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Titel: III-V Nanowires for High-Speed Electronics

Author: Markus HellenbrandDepartment of Electrical and Information Technology

Faculty opponent: Professor Tibor Grasser, TU Wienna

When: 12 June at 9:15

Location:  E:1406, E-building, Ole Römers väg 3, LTH, Lund University / Zoom: https://lu-se.zoom.us/j/64523497259 

Link to: interview with Markus Hellenbrand: In support of current control by quantum-mechanical tunnelling

Thesis abstract: The ever increasing demand for faster and more energy-efficient electrical computation and communication presents severe challenges for the semiconductor industry and particularly for the metal-oxidesemiconductor field-effect transistor (MOSFET), which is the workhorse of modern electronics. III-V materials exhibit higher carrier mobilities than the most commonly used MOSFET material Si so that the realisation of III-V MOSFETs can enable higher operation speeds and lower drive voltages than that which is possible in Si electronics. A lowering of the transistor drive voltage can be further facilitated by employing gate-all-around nanowire geometries or novel operation principles. However, III-V materials bring about their own challenges related to material quality and to the quality of the gate oxide on top of a III-V MOSFET channel.

This thesis presents detailed electrical characterisations of two types of (vertical) III-V nanowire transistors: MOSFETs based on conventional thermionic emission; and Tunnel FETs, which utilise quantum-mechanical tunnelling instead to control the device current and reach inverse subthreshold slopes below the thermal limit of 60 mV/decade. Transistor characterisations span over fourteen orders of magnitude in frequency/time constants and temperatures from 11 K to 370 K.

The first part of the thesis focusses on the characterisation of electrically active material defects (‘traps’) related to the gate stack. Low-frequency noise measurements yielded border trap densities of 10^18 to 10^20 cm^-3 eV^-1 and hysteresis measurements yielded effective trap densities – projected to the oxide/semiconductor interface – of 2x10^12 to 3x10^13 cm^-2 eV^-1. Random telegraph noise measurements revealed that individual oxide traps can locally shift the channel energy bands by a few millielectronvolts and that such defects can be located at energies from inside the semiconductor band gap all the way into the conduction band.

Small-signal radio frequency (RF) measurements revealed that parts of the wide oxide trap distribution can still interact with carriers in the MOSFET channel at gigahertz frequencies. This causes frequency hystereses in the small-signal transconductance and capacitances and can decrease the RF gains by a few decibels. A comprehensive small-signal model was developed, which takes into account these dispersions, and the model was applied to guide improvements of the physical structure of vertical RF MOSFETs. This resulted in values for the cutoff frequency fT and the maximum oscillation frequency fmax of about 150 GHz in vertical III-V nanowire MOSFETs.

Bias temperature instability measurements and the integration of (lateral) III-V nanowire MOSFETs in a back end of line process were carried out as complements to the main focus of this thesis. The results of this thesis provide a broad perspective of the properties of gate oxide traps and of the RF performance of III-V nanowire transistors and can act as guidelines for further improvement and finally the integration of III-V nanowire MOSFETs in circuits.

Thesis for download