Electrical and Information Technology

Faculty of Engineering, LTH

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PhD defence:Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications


From: 2021-09-17 09:15 to 12:00
Place: Online - and/or E:1406, E-huset, Ole Römers väg 3, LTH, Lund University, Lund.
Contact: lars-erik [dot] wernersson [at] eit [dot] lth [dot] se
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Thesis title: Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications

Author: Adam Jönsson Department of Electrical and Information Technology, Lund university

Faculty opponent: Opponent är professor Aaron Voon-Yew Thean, Singapore universitet, Singapore.

Location: Online - link by registration and/or E:B E-huset, Ole Römers väg 3, LTH, Lund University, Lund.


This thesis focuses mainly on the co-integration of vertical nanowire n-type InAs and p-type GaSb MOSFETs on Si (Paper I & II), where MOVPE grown vertical InAs-GaSb heterostructure nanowires are used for realizing monolithically integrated and co-processed all-III-V CMOS. Utilizing a bottom-up approach based on MOVPE grown nanowires enables design flexibilities, such as in-situ doping and heterostructure formation, which serves to reduce the amount of mask steps during fabrication. By refining the fabrication techniques, using a self-aligned gate-last process, scaled 10-20 nm diameters are achieved for balanced drive currents at Ion ∼ 100 μA/μm, considering Ioff at 100 nA/μm (VDD = 0.5 V). This is enabled by greatly improved p-type MOSFET performance reaching a maximum transconductance of 260 μA/μm at VDS = 0.5 V. Lowered power dissipation for CMOS circuits requires good threshold voltage VT matching of the n- and p-type device, which is also demonstrated for basic inverter circuits. The various effects contributing to VT-shifts are also studied in detail focusing on the InAs channel devices (with highest transconductance of 2.6 mA/μm), by using Electron Holography and a novel gate position variation method (Paper V).

The advancements in all-III-V CMOS integration spawned individual studies into the strengths of the n- and p-type III-V devices, respectively. Traditionally materials such as InAs and InGaAs provide excellent electron transport properties, therefore they are frequently used in devices for high frequency RF applications. In contrast, the III-V p-type alternatives have been lacking performance mostly due to the difficult oxidation properties of Sb-based materials. Therefore, a study of the GaSb properties, in a MOSFET channel, was designed and enabled by new manufacturing techniques, which allowed gate-length scaling from 40 to 140 nm for p-type Sb-based MOSFETs (Paper III). The new fabrication method allowed for integration of devices with symmetrical contacts as compared to previous work which relied on a tunnel-contact at the source-side. By modelling based on measured data fieldeffect hole mobility of 70 cm2/Vs was calculated, well in line with previously reported studies on GaSb nanowires. The oxidation properties of the GaSb gate-stack was further characterized by XPS, where high intensities of xrays are achieved using a synchrotron source allowed for characterization of nanowires (Paper VI). Here, in-situ H2-plasma treatment, in parallel with XPS measurements, enabled a study of the time-dependence during full removal of GaSb native oxides.

The last focus of the thesis was building on the existing strengths of vertical heterostructure III-V n-type (InAs-InGaAs graded channel) devices. Typically, these devices demonstrate high-current densities (gm >3 mS/μm) and excellent modulation properties (off-state current down to 1 nA/μm). However, minimizing the parasitic capacitances, due to various overlaps originating from a low access-resistance design, has proven difficult. Therefore, new methods for spacers in both the vertical and planar directions was developed and studied in detail. The new fabrication methods including sidewall spacers achieved gate-drain capacitance CGD levels close to 0.2 fF/μm, which is the established limit by optimized high-speed devices. The vertical spacer technology, using SiO2 on the nanowire sidewalls, is further improved in this thesis which enables new co-integration schemes for memory arrays. Namely, the refined sidewall spacer method is used to realize selective recess etching of the channel and reduced capacitance for large array memory selector devices (InAs channel) vertically integrated with Resistive Random Access Memory (RRAM) memristors. (Paper IV) The fabricated 1-transistor-1- memristor (1T1R) demonstrator cell shows excellent endurance and retention for the RRAM by maintaining constant ratio of the high and low resistive state (HRS/LRS) after 106 switching cycles.


The event is open to anyone interested. If you register at we send you a link for the event at the zoom platform.