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Licentiate Thesis seminar: Blocker-Tolerant Continuous-Time Delta-Sigma Modulator for Wireless Communication by Xiaodong Liu


Tid: 2017-11-20 10:00 till: 12:00
Plats:E:3139, Institutionen för Elektro- och informationsteknik, E-huset, LTH

Title: Blocker-Tolerant Continuous-Time Delta-Sigma Modulator for Wireless Communication

Presentetd by: Xiaodong Liu

When: November 20, 2017 10:00

Place: E:3139, Institutionen för Elektro- och informationsteknik, E-huset, LTH
Special reviewer:
Lektor Harish Krishnaswamy, Columbia University, New York, USA
Supervisor: Universitetslektor Pietro Andreani, EIT
Examinator: Universitetslektor Joachim Rodrigues, EIT
The wireless communication industry has witnessed explosive growth over the last decade. The spread of mobile devices like smartphones demands power efficient receiver front-end with high level of integration in cost efficient semiconductor technology like CMOS process, which makes the direct conversion receiver a dominant receiver architecture in the mobile communication for its reduced number of filtering and frequency translating stages. As high data rate demands larger bandwidth and the lack of filtering necessities high dynamic range, continuous-time (CT) Delta-Sigma modulator (DSM) has become a compelling choice for implementing the analog-to-digital converters (ADCs) to enable a power efficient wireless receiver.

This thesis investigates the design of CT DSM ADC for wireless communication from two perspectives. The first perspective is to map the full scale of DSM's quantizer to the less filtered blockers level and optimize the quantization noise performance of CT DSM so that the blockers are accommodated within the dynamic range of DSM. The second perspective is to incorporate the ADC with the filter through global feedbacks, which results in an A/D channel-select filter (ADCSF). Therefore the strong blockers are sufficiently attenuated before they present at the quantizer input. Moreover, the global feedbacks provide additional shaping of ADC noise, which can be utilized to optimize the power/noise performance.

Both approaches are implemented in 65nm CMOS process and practical design considerations are discussed in the thesis. The first prototype achieves 64 dB dynamic range and consumes 9mA from 1.2V power supply, which result in a figure-of-merit (FOM) of 225 fJ/conversion. The second prototype has a 4th-order Butterworth filter response with the cut-off frequency at only 1.36 times the signal bandwidth to achieve a sharp filtering. The additional noise shaping on the quantization noise provided by the global feedbacks is around 23 dB. The second prototype is also integrated into the single chip direct conversion receiver where the RF-to-digital performance is fully characterized. The receiver with ADCSF demonstrates overall state-of-the-art performance.