Thesis defence: Zhongyunshen Zhu

Disputation

Tid: 2023-10-13 09:15 till 13:00
Plats: Lecture hall E:1406, Ole Römers väg 3, Lund
Kontakt: zhongyunshen [dot] zhu [at] eit [dot] lth [dot] se

Vertical III-V Nanowire Transistors for Low-Power Logic and Reconfigurable Applications

With rapid increase in energy consumption of electronics used in our daily life, the building blocks — transistors — need to work in a way that has high energy efficiency and functional density to meet the demand of further scaling. III-V channel combined with vertical nanowire gate-all-around (GAA) device architecture is a promising alternative to conventional Si transistors due to its excellent electrical properties in the channel and electrostatic control across the gate oxide in addition to reduced footprint. Based on this platform, two major objectives of this thesis are included: 1) to improve the performance of III-V p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and tunnel FETs (TFETs) for low-power digital applications; 2) to integrate HfO2-based ferroelectric gate onto III-V FETs (FeFETs) and TFETs (ferro-TFETs) to enable reconfigurable operation for high functional density..

Link to thesis in LU Research Portal.

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