PhD defence: Vertical III-V Nanowires For In-Memory Computing via Heterogeneous Integration-Rapid Melt Growth and Template Assisted Selective Epitaxy - Cloned

Disputation

Tid: 2023-09-01 09:15 till 13:00
Plats: E:B, E-huset, Ole Römers väg 3, LTH, Lund University, Lund, and online
Kontakt: saketh_ram [dot] mamidala [at] eit [dot] lth [dot] se

Title: Vertical III-V Nanowires For In-Memory Computing

Author: Saketh Ram Mamidala, Department of Electrical and Information Technology, Lund University

Location: E:B E-huset, Ole Römers väg 3, LTH, Lund University, Lund.

Link to thesis.

Zoom:
https://lu-se.zoom.us/s/64202896244

Abstract

In recent times, deep neural networks (DNNs) have demonstrated great potential in various machine learning applications,
such as image classification and object detection for autonomous driving. However, increasing the accuracy of DNNs
requires scaled, faster, and more energy-efficient hardware, which is limited by the von Neumann architecture where
separate memory and computing units lead to a bottleneck in performance. A promising solution to address the von
Neumann bottleneck is in-memory computing, which can be achieved by integrating non-volatile memory cells such as
RRAMs into dense crossbar arrays. On the hardware side, the 1-transistor-1-resistor (1T1R) configuration has been central
to numerous demonstrations of reservoir, in-memory and neuromorphic computing.

In this thesis, to achieve a 1T1R cell with a minimal footprint of 4F², a technology platform has been developed to integrate a
vertical nanowire GAA MOSFET as a selector device for the RRAM. Firstly, the effect of the geometry (planar to vertical) of
the ITO/HfO₂/TiN RRAM cell was studied where low energy switching (0.49 pJ) and high endurance (10⁶) were achieved
in the vertical configuration. Furthermore, InAs was incorporated as the GAA MOSFET selector channel material to
leverage the beneficial transport properties of III-V materials desirable for supply voltage scaling. Finally, an approach was
developed wherein InAs is used as the selector channel as well as the RRAM electrode by carefully tuning the InAs native
oxides. This thesis also presents low-frequency noise characterization of the RRAM cell as well as the MOSFET to further
understand the semiconductor/oxide interface. The vertical 1T1R cell developed in this thesis enables the implementation
of Boolean logic operations using a single vertical nanowire while reducing the footprint by 51x when compared to its
traditional CMOS counterpart.