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PhD Defence: III-V Nanowires for High-Speed Electronics (Fredrik Lindelöw)


From: 2020-05-20 09:15
Place: E:1406, E-building, Ole Römers väg 3, LTH, Lund University / Zoom:
Contact: erik [dot] lind [at] eit [dot] lth [dot] se
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Titel: III-V Nanowires for High-Speed Electronics

Author: Fredrik Lindelöw,  Department of Electrical and Information Technology

Faculty opponent: Dr. Nadine Collaert, Belgien

When: 20 May at 9:15

Location:  E:1406, E-building, Ole Römers väg 3, LTH, Lund University / Zoom: 

Thesis abstract: III-V compound materials have long been used in RF applications in high-electron-mobility-transistors (HEMTs) and bipolar-junction-transistors (BJTs). Now, III-V is also being viewed as a material candidate for replacing silicon in the n-channel in CMOS processes for increased drive currents and reduced power consumption in future nodes. Another alternative to increase the drive current is to use nanowire channels, where the increased electrostatic control can be utilized for scaling the gate length even further. In this thesis, we have characterized III-V nanowires with Hall-measurements to quantify the carrier concentration and optimize growth parameters. We have fabricated nanowire transistors for both digital and analog applications. Digital transistors made of a single nanowire show state-of-the art performance with low subthreshold slope and simultaneously high transconductance and high on-current. For RF applications, the nanowire technology faces several challenges, mainly due to its inherent higher parasitic capacitance since the filling factor is less than 1. To adapt the DC processing scheme to RF measurements, we have implemented T-gates, two-finger devices, 100 nanowires in parallel with tight pitch and we have developed novel spacer schemes with capacitances almost as low as recessed HEMT devices. These schemes consists of for instance modulation doped InP spacers as well as self-aligned air-spacers. To make the RF nanowire MOSFETs even more competitive, the transoncductance of RF devices needs to be optimized to match that of DC devices.

Thesis for download